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ispLSI and pLSI 1016E
(R) (R)
High-Density Programmable Logic Features
* HIGH-DENSITY PROGRAMMABLE LOGIC -- 2000 PLD Gates -- 32 I/O Pins, Four Dedicated Inputs -- 96 Registers -- High-Speed Global Interconnect -- Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. -- Small Logic Block Size for Random Logic * HIGH-PERFORMANCE E2CMOS(R) TECHNOLOGY -- fmax = 125 MHz Maximum Operating Frequency -- tpd = 7.5 ns Propagation Delay -- TTL Compatible Inputs and Outputs -- Electrically Erasable and Reprogrammable -- Non-Volatile -- 100% Tested at Time of Manufacture -- Unused Product Term Shutdown Saves Power * ispLSI OFFERS THE FOLLOWING ADDED FEATURES -- In-System ProgrammableTM (ISPTM) 5-Volt Only -- Increased Manufacturing Yields, Reduced Time-toMarket and Improved Product Quality -- Reprogram Soldered Device for Faster Prototyping * OFFERS THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FIELD PROGRAMMABLE GATE ARRAYS -- Complete Programmable Device Can Combine Glue Logic and Structured Designs -- Enhanced Pin Locking Capability -- Three Dedicated Clock Input Pins -- Synchronous and Asynchronous Clocks -- Programmable Output Slew Rate Control to Minimize Switching Noise -- Flexible Pin Placement -- Optimized Global Routing Pool Provides Global Interconnectivity * pLSI/ispLSI DEVELOPMENT TOOLS pDS(R) Software -- Easy to Use PC WindowsTM Interface -- Boolean Logic Compiler -- Manual Partitioning -- Automatic Place and Route -- Static Timing Table ispDS+TM Software -- Industry Standard, Third-Party Design Environments -- Schematic Capture, State Machine, HDL -- Automatic Partitioning and Place and Route -- Comprehensive Logic and Timing Simulation -- PC and Workstation Platforms
Functional Block Diagram
A0
B7 B5
GLB
Output Routing Pool
A2 A3 A4 A5 A6 A7
Logic Array
DQ
DQ
B4 B3 B2 B1
DQ
Global Routing Pool (GRP)
B0 CLK
Description
The ispLSI and pLSI 1016E are High-Density Programmable Logic Devices containing 96 Registers, 32 Universal I/O pins, four Dedicated Input pins, three Dedicated Clock Input pins, one Global OE input pin and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The ispLSI 1016E features 5-Volt in-system programming and in-system diagnostic capabilities. The ispLSI 1016E offers non-volatile "on-the-fly" reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. It is architecturally and parametrically compatible to the pLSI 1016E device, but multiplexes four input pins to control in-system programming. A functional superset of the ispLSI and pLSI 1016 architecture, the ispLSI and pLSI 1016E devices add a new global output enable pin. The basic unit of logic on the ispLSI and pLSI 1016E devices is the Generic Logic Block (GLB). The GLBs are labeled A0, A1...B7 (see figure 1). There are a total of 16 GLBs in the ispLSI and pLSI 1016E devices. Each GLB has 18 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any other GLB on the device.
Copyright (c) 1997 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A. Tel. (503) 681-0118; 1-800-LATTICE; FAX (503) 681-3037; http://www.latticesemi.com
February 1997 1996 ISP Encyclopedia
1016E_04
Output Routing Pool
0139C1-isp
A1
DQ
B6
Specifications ispLSI and pLSI 1016E
Functional Block Diagram
Figure 1. ispLSI and pLSI 1016E Functional Block Diagram
Generic Logic Blocks (GLBs) GOE 0/IN 3 MODE*/IN 2 B7 I/O 0 I/O 1 I/O 2 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7 I/O 8 I/O 9 I/O 10 I/O 11 I/O 12 I/O 13 I/O 14 I/O 15 *SDI/IN 0 *SDO/IN 1 A0 A1 B6 I/O 31 I/O 30 I/O 29 I/O 28
Output Routing Pool (ORP)
B5 B4 B3 B2 B1 B0
Output Routing Pool (ORP)
Input Bus
A3 A4 A5 A6 A7
Global Routing Pool (GRP)
lnput Bus
A2
I/O 27 I/O 26 I/O 25 I/O 24 I/O 23 I/O 22 I/O 21 I/O 20 I/O 19 I/O 18 I/O 17 I/O 16
Clock Distribution Network
CLK 0 CLK 1 CLK 2 IOCLK 0 IOCLK 1
Megablock
*ispEN/NC * ispLSI 1016E Only
Y0 Y1** *SCLK/Y2
**Note: Y1 and RESET are multiplexed on the same pin
0139B(1a)-isp
The devices also have 32 I/O cells, each of which is directly connected to an I/O pin. Each I/O cell can be individually programmed to be a combinatorial input, registered input, latched input, output or bi-directional I/O pin with 3-state control. The signal levels are TTL compatible voltages and the output drivers can source 4 mA or sink 8 mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Eight GLBs, 16 I/O cells, two dedicated inputs and one ORP are connected together to make a Megablock (see figure 1). The outputs of the eight GLBs are connected to a set of 16 universal I/O cells by the ORP. Each ispLSI and pLSI 1016E device contains two Megablocks.
The GRP has, as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional I/O cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the ispLSI and pLSI 1016E devices are selected using the Clock Distribution Network. Three dedicated clock pins (Y0, Y1 and Y2) are brought into the distribution network, and five clock outputs (CLK 0, CLK 1, CLK 2, IOCLK 0 and IOCLK 1) are provided to route clocks to the GLBs and I/O cells. The Clock Distribution Network can also be driven from a special clock GLB (B0 on the ispLSI and pLSI 1016E devices). The logic of this GLB allows the user to create an internal clock from a combination of internal signals within the device.
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
Absolute Maximum Ratings 1
Supply Voltage VCC ................................. -0.5 to +7.0V Input Voltage Applied ........................ -2.5 to VCC +1.0V Off-State Output Voltage Applied ..... -2.5 to VCC +1.0V Storage Temperature ................................ -65 to 150C Case Temp. with Power Applied .............. -55 to 125C Max. Junction Temp. (TJ) with Power Applied ... 150C
1. Stresses above those listed under the "Absolute Maximum Ratings" may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specifica tion is not implied (while programming, follow the programming specifications).
DC Recommended Operating Conditions
SYMBOL PARAMETER Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial TA = 0C to + 70C TA = -40C to + 85C MIN. 4.75 4.5 0 2.0 MAX. 5.25 5.5 0.8 Vcc+1 UNITS V V V V
Table 2-0005/1016E
VCC VIL VIH
Capacitance (TA=25oC, f=1.0 MHz)
SYMBOL PARAMETER Dedicated Input, I/O, Y1, Y2, Y3, Clock Capacitance (Commercial/Industrial) Y0 Clock Capacitance TYPICAL 8 12 UNITS pf pf TEST CONDITIONS VCC = 5.0V, VPIN = 2.0V VCC = 5.0V, VPIN = 2.0V
Table 2-0006/1016E
C1 C2
Data Retention Specifications
PARAMETER Data Retention ispLSI Erase/Reprogram Cycles pLSI Erase/Reprogram Cycles MINIMUM 20 10000 100 MAXIMUM - - - UNITS Years Cycles Cycles
Table 2-0008/1016E
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
Switching Test Conditions
Input Pulse Levels Input Rise and Fall Time 10% to 90% Input Timing Reference Levels Ouput Timing Reference Levels Output Load 3-state levels are measured 0.5V from steady-state active level. GND to 3.0V -125 -100, -80 1.5V 1.5V See figure 2
Table 2-0003/1016E
Figure 2. Test Load
2 ns 3 ns
+ 5V R1 Device Output R2 CL* Test Point
Output Load Conditions (see figure 2)
TEST CONDITION A B Active High Active Low Active High to Z at VOH -0.5V Active Low to Z at VOL +0.5V R1 470 470 470 R2 390 390 390 390 390 CL 35pF 35pF 35pF 5pF 5pF
*CL includes Test Fixture and Probe Capacitance.
0213a
C
Table 2-0004/1016E
DC Electrical Characteristics
Over Recommended Operating Conditions
SYMBOL PARAMETER Output Low Voltage Output High Voltage Input or I/O Low Leakage Current Input or I/O High Leakage Current ispEN Input Low Leakage Current I/O Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current IOL= 8 mA IOH = -4 mA 0V VIN VIL (Max.) 3.5V VIN VCC 0V VIN VIL 0V VIN VIL VCC = 5V, VOUT = 0.5V VIL = 0.5V, VIH = 3.0V fCLOCK = 1 MHz Commercial Industrial CONDITION MIN. - 2.4 - - - - - - - TYP. - - - - - - - 90 90
3
MAX. UNITS 0.4 - -10 10 -150 -150 -200 - - V V A A A A mA mA mA
VOL VOH IIL IIH IIL-isp IIL-PU IOS1 ICC2, 4
Table 2-0007/1016E
1. One output at a time for a maximum duration of one second. VOUT = 0.5V was selected to avoid test problems by tester ground degradation. Guaranteed but not 100% tested. 2. Measured using four 16-bit counters. 3. Typical values are at VCC = 5V and TA= 25C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book to estimate maximum I CC .
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
External Timing Parameters
Over Recommended Operating Conditions
PARAMETER TEST 2 # COND. A A A - - - A - - - - A - B C B C - - - -
4
DESCRIPTION1
-125 - - 125
1 tsu2 + tco1
-100 - - 100 77 125 7.0 - 0.0 8.0 - 0.0 - 6.5 - - - - 4.0 4.0 3.5 0.0 10.0 13.0 - - - - 5.0 - - 6.0 - 13.5 - 15.0 15.0 9.0 9.0 - - - - - -
-80 UNITS ns ns MHz MHz MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 15.0 18.5 - - - - 8.0 - - 9.5 - 17.0 - 20.0 20.0 10.5 10.5 - - - -
MIN. MAX. MIN. MAX. MIN. MAX. 7.5 10.0 - - - - 4.5 - - 5.5 - 10.0 - 12.0 12.0 7.0 7.0 - - - -
tpd1 tpd2 fmax fmax (Ext.) fmax (Tog.) tsu1 tco1 th1 tsu2 tco2 th2 tr1 trw1 tptoeen tptoedis tgoeen tgoedis twh twl tsu3 th3
1. 2. 3. 4.
1 Data Prop. Delay, 4PT Bypass, ORP Bypass 2 Data Prop. Delay, Worst Case Path 3 Clk. Frequency with Int. Feedback 5 Clk. Frequency, Max. Toggle(
3
84.0 57.0 100 8.5 - 0.0 9.5 - 0.0 - 10.0 - - - - 5.0 5.0 4.5 0.0
4 Clk. Frequency with Ext. Feedback(
)
100 167 5.0 - 0.0 5.5 - 0.0 - 5.0 - - - - 3.0 3.0 0.0
1 twh + tw1
)
6 GLB Reg. Setup Time before Clk., 4 PT Bypass 7 GLB Reg. Clk. to Output Delay, ORP Bypass 8 GLB Reg. Hold Time after Clk., 4 PT Bypass 9 GLB Reg. Setup Time before Clk. 10 GLB Reg. Clk. to Output Delay 11 GLB Reg. Hold Time after Clk. 12 Ext. Reset Pin to Output Delay 13 Ext. Reset Pulse Duration 14 Input to Output Enable 15 Input to Output Disable 16 Global OE Output Enable 17 Global OE Output Disable 18 Ext. Sync. Clk. Pulse Duration, High 19 Ext. Sync. Clk. Pulse Duration, Low 21 I/O Reg. Hold Time after Ext. Sync. Clk. (Y2, Y3)
20 I/O Reg. Setup Time before Ext. Sync. Clk. (Y2, Y3) 3.0
Unless noted otherwise, all parameters use the GRP, 20 PTXOR path, ORP and Y0 clock. Refer to Timing Model in this data sheet for further details. Standard 16-bit counter using GRP feedback. Reference Switching Test Conditions Section.
Table 2-0030-16/125,100, 80
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
Internal Timing Parameters1
PARAMETER #
2
DESCRIPTION
-125
-100
-80
MIN. MAX. MIN. MAX. MIN. MAX. - - 3.0 -0.3 - - - - - - - - - - - - - 0.2 1.5 - - - - 3.2 - - 0.3 1.8 - - 4.0 4.0 2.2 1.8 1.9 2.1 2.4 3.9 3.9 4.4 4.4 4.4 1.0 - - 1.8 4.4 3.5 5.5 3.5 1.0 0.0 - - 3.5 -0.4 - - - - - - - - - - - - - 0.2 2.5 - - - - 4.8 - - 0.4 2.4 - - 5.0 5.0 2.6 1.9 2.2 2.5 3.1 5.7 5.6 6.1 6.1 6.6 1.6 - - 1.9 6.3 5.1 7.1 5.3 1.0 0.0 - - 4.5 -0.6 - - - - - - - - - - - - - -0.6 4.3 - - - - 6.8 - - 0.6 3.6 - - 7.5 7.5 3.9
UNITS
Inputs
tiobp tiolat tiosu tioh tioco tior tdin
GRP
22 I/O Register Bypass 23 I/O Latch Delay 24 I/O Register Setup Time before Clock 25 I/O Register Hold Time after Clock 26 I/O Register Clock to Out Delay 27 I/O Register Reset to Out Delay 28 Dedicated Input Delay 29 GRP Delay, 1 GLB Load 30 GRP Delay, 4 GLB Loads 31 GRP Delay, 8 GLB Loads 32 GRP Delay, 16 GLB Loads 34 4 Product Term Bypass Path Delay (Combinatorial) 35 4 Product Term Bypass Path Delay (Registered) 36 1 Product Term/XOR Path Delay 37 20 Product Term/XOR Path Delay 38 XOR Adjacent Path Delay 3 39 GLB Register Bypass Delay 40 GLB Register Setup Time before Clock 41 GLB Register Hold Time after Clock 42 GLB Register Clock to Output Delay 43 GLB Register Reset to Output Delay 44 GLB Product Term Reset to Register Delay 45 GLB Product Term Output Enable to I/O Cell Delay 46 GLB Product Term Clock Delay 47 ORP Delay 48 ORP Bypass Delay
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
tgrp1 tgrp4 tgrp8 tgrp16
GLB
2.9 3.3 3.8 4.7 8.1 7.3 7.1 8.2 8.3 1.9 - - 2.9 7.0 7.2 9.7 7.5 1.5 0.0
t4ptbpc t4ptbpr t1ptxor t20ptxor txoradj tgbp tgsu tgh tgco tgro tptre tptoe tptck
ORP
torp torpbp
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details. 3. The XOR Adjacent path can only be used by Lattice hard macros.
Table 2-0036-16/125,100, 80
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
Internal Timing Parameters1
PARAMETER #
2
DESCRIPTION
-125
-100
-80 UNITS
MIN. MAX. MIN. MAX. MIN. MAX. - - - - - 1.4 10.0 4.3 4.3 2.7 - - - - - 1.7 10.0 5.3 5.3 3.7 - - - - - 2.1 3.6 1.2 0.0 1.2 - 3.0 10.0 6.4 6.4 4.1 2.1 4.4 2.7 0.6 2.7 5.5
Outputs
tob tsl toen todis tgoe
Clocks
49 Output Buffer Delay 50 Output Slew Limited Delay Adder 51 I/O Cell OE to Output Enabled 52 I/O Cell OE to Output Disabled 53 Global Output Enable 54 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) 55 Clock Delay, Y1 or Y2 to Global GLB Clock Line 56 Clock Delay, Clock GLB to Global GLB Clock Line 57 Clock Delay, Y1 or Y2 to I/O Cell Global Clock Line 58 Clock Delay, Clock GLB to I/O Cell Global Clock Line 59 Global Reset to GLB and I/O Registers
ns ns ns ns ns ns ns ns ns ns ns
tgy0 tgy1/2 tgcp tioy1/2 tiocp tgr
1.3 2.3 0.8 0.0 0.8 -
1.3 2.7 1.8 0.3 1.8 3.2
1.4 2.4 0.8 0.0 0.8 -
1.4 2.9 1.8 0.4 1.8 4.5
Global Reset
1. Internal Timing Parameters are not tested and are for reference only. 2. Refer to Timing Model in this data sheet for further details.
Table 2-0037-16/125,100,80
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
ispLSI and pLSI 1016E Timing Model
I/O Cell GRP Feedback Ded. In Comb 4 PT Bypass #34 Reg 4 PT Bypass #30 GRP Loading Delay #29, 31, 32 #35 20 PT XOR Delays #36-38 #59 D RST Reset #40-43 GLB Reg Bypass #39 GLB Reg Delay Q ORP Bypass #48 ORP Delay #47 #49, 50 #51, 52 I/O Pin (Output) GLB ORP I/O Cell
#28 I/O Reg Bypass #22 Input D Register Q RST #23 - 27
I/O Pin (Input)
#59
Clock Distribution Y1,2 #55-58
Control RE PTs OE #44-46 CK
Y0 GOE 0
#54
0491-16
#53
Derivations of tsu, th and tco from the Product Term Clock 1 tsu
= = = 1.4 ns = = = = 0.6 ns = = = = 9.9 ns = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tiobp + tgrp4 + tptck(min)) (#22 + #30 + #37) + (#40) - (#22 + #30 + #46) (0.3 + 1.9 + 4.4) + (0.2) - (0.3 + 1.9 + 3.2) Clock (max) + Reg h - Logic (tiobp + tgrp4 + tptck(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#22 + #30 + #46) + (#41) - (#22 + #30 + #37) (0.3 + 1.9 + 3.5) + (1.5) - (0.3 + 1.9 + 4.4) Clock (max) + Reg co + Output (tiobp + tgrp4 + tptck(max)) + (tgco) + (torp + tob) (#22 + #30 + #46) + (#42) + (#47 + #49) (0.3 + 1.9 + 3.5) + (1.8) + (1.0 + 1.4)
th
tco
Derivations of tsu, th and tco from the Clock GLB 1 tsu
= = = 2.9 ns = = = = -0.2 ns = = = = 9.1 ns = Logic + Reg su - Clock (min) (tiobp + tgrp4 + t20ptxor) + (tgsu) - (tgy0(min) + tgco + tgcp(min)) (#22 + #30 + #37) + (#40) - (#54 + #42 + #56) (0.3 + 1.9 + 4.4) + (0.2) - (1.3 + 1.8 + 0.8) Clock (max) + Reg h - Logic (tgy0(max) + tgco + tgcp(max)) + (tgh) - (tiobp + tgrp4 + t20ptxor) (#54 + #42 + #56) + (#41) - (#22 + #30 + #37) (1.3 + 1.8 + 1.8) + (1.5) - (0.3 + 1.9 + 4.4) Clock (max) + Reg co + Output (tgy0(max) + tgco + tgcp(max)) + (tgco) + (torp + tob) (#54 + #42 + #56) + (#42) + (#47 + #49) (1.3 + 1.8 + 1.8) + (1.8) + (1.0 + 1.4)
Table 2-0042-16
th
tco
1. Calculations are based upon timing specifications for the ispLSI and pLSI 1016E-125
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
Maximum GRP Delay vs GLB Loads
3 ispLSI and pLSI 1016E-80 ispLSI and pLSI 1016E-100
GRP Delay (ns)
2 ispLSI and pLSI 1016E-125 1
1
4
8 GLB Load
12
16
16E GRP/GLB.eps
Power Consumption
Power Consumption in the ispLSI and pLSI 1016E device depends on two primary factors: the speed at which the device is operating and the number of Product Terms Figure 3. Typical Device Power Consumption vs fmax
130 120 110
ispLSI and pLSI 1016E
used. Figure 3 shows the relationship between power and operating speed.
ICC (mA)
100 90 80 0 20 40 60 80 100 120 140
fmax (MHz)
Notes: Configuration of four 16-bit counters Typical current at 5V, 25C
ICC can be estimated for the ispLSI and pLSI 1016E using the following equation: ICC(mA) = 23 + (# of PTs * 0.52) + (# of nets * max freq * 0.004) Where: # of PTs = Number of product terms used in design # of nets = Number of signals used in device Max freq = Highest clock frequency to the device (in MHz) The ICC estimate is based on typical conditions (VCC = 5.0V, room temperature) and an assumption of four GLB loads on average exists and the device is filled with four 16-bit counters. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified.
0127B-16-80-isp/1016
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
In-System Programmability
The ispLSI devices are the in-system programmable versions of the Lattice Semiconductor High-Density Programmable Large Scale Integration (pLSI) devices. By integrating all the high voltage programming circuitry onchip, programming can be accomplished by simply shifting data into the device. Once the function is programmed, the non-volatile E2CMOS cells will not lose the pattern even when the power is turned off. All necessary programming is done via five TTL level logic interface signals. These five signals are fed into the on-chip programming circuitry where a state machine controls the programming. The simple signals for the interface include isp Enable (ispEN), Serial Data In (SDI), Serial Data Out (SDO), Serial Clock (SCLK) and Mode (MODE) control. Figure 4 illustrates the block diagram of one possible scheme for programming the ispLSI devices. For details on the operation of the internal state machine and programming of the device, please refer to the ISP Architecture and Programming section of the 1996 Lattice Data Book. The device identifier for the ispLSI 1016E is 0000 1011 (0B hex). This code is the unique device identifier which is generated when a read ID command is performed.
Figure 4. ISP Programming Interface
SDO SDI MODE SCLK ispEN
5-wire ISP Programming Interface
ispEN SCLK MODE
SCLK MODE
SCLK MODE
ispEN SCLK MODE
ispLSI
SDI SDO
ispGAL
SDI SDO
ispGDS
SDI SDO SDI
ispLSI
SDO
0294B
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1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
ispLSI 1016E Shift Register Layout
D A T A Data In (SDI) 79... 159... High Order Shift Register Low Order Shift Register
D A T A ...0 ...80 109 . . . SDO SDI
E2CMOS Cell Array
Address Shift Register
. . . 0
0182B-16
SDO
Note: A logic "1" in the Address Shift Register bit position enables the row for programming or verification. A logic "0" disables it.
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Specifications ispLSI and pLSI 1016E
Pin Description
NAME I/O 0 - I/O 3 I/O 4 - I/O 7 I/O 8 - I/O 11 I/O 12 - I/O 15 I/O 16 - I/O 19 I/O 20 - I/O 23 I/O 24 - I/O 27 I/O 28 - I/O 31 GOE 0/IN 3 ispEN**/NC PLCC PIN NUMBERS 15, 19, 25, 29, 37, 41, 3, 7, 2 13 16, 20, 26, 30, 38, 42, 4, 8, 17, 21, 27, 31, 39, 43, 5, 9, 18, 22, 28, 32, 40, 44, 6, 10 TQFP PIN NUMBERS 9, 13, 19, 23, 31, 35, 41, 1, 40 7 10, 14, 20, 24, 32, 36, 42, 2, 11, 15, 21, 25, 33, 37, 43, 3, 12, 16, 22, 26, 34, 38, 44, 4 DESCRIPTION
Input/Output Pins - These are the general purpose I/O pins used by the logic array.
This is a dual function pin. It can be used either as Global Output Enable for all I/O cells or it can be used as a dedicated input pin. Input - Dedicated in-system programming enable input pin. This pin is brought low to enable the programming mode. The MODE, SDI, SDO and SCLK controls become active. Input - This pin performs two functions. When ispEN is logic low, it functions as an input pin to load programming data into the device. It is a dedicated input pin when ispEN is logic high.SDI/IN0 also is used as one of the two control pins for the isp state machine.
SDI*/IN 0
14
8
MODE*/IN 2
36
30
Input - This pin performs two functions. When ispEN is logic low, it functions as a pin to control the operation of the isp state machine. It is a dedicated input pin when ispEN is logic high. Output/Input - This pin performs two functions. When ispEN is logic low, it functions as an ouput pin to read serial shift register data. It is a dedicated input pin when ispEN is logic high. Input - This pin performs two functions. When ispEN is logic low, it functions as a clock pin for the Serial Shift Register. It is a dedicated clock input when ispEN is logic high. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device.
Dedicated Clock input. This clock input is connected to one of the clock inputs of all the GLBs on the device. This pin performs two functions: - Dedicated clock input. This clock input is brought into the Clock Distribution Network, and can optionally be routed to any GLB and/or I/O cell on the device. - Active Low (0) Reset pin which resets all of the GLB and I/O registers in the device.
SDO*/IN 1
24
18
SCLK*/Y2
33
27
Y0 Y1/RESET
11 35
5 29
GND VCC
1,
23
17, 39 6, 28
Ground (GND) Vcc
Table 2-0002C-16-isp
12, 34
* ispLSI 1016E only ** ispEN for ispLSI 1016E; NC for pLSI 1016E must be left floating or tied to Vcc, must not be grounded or tied to any other signal.
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Specifications ispLSI and pLSI 1016E
Pin Configurations
ispLSI and pLSI 1016E 44-pin PLCC Pinout Diagram
I/O 27 I/O 26 I/O 25 I/O 24 **GOE 0/IN 3 GND I/O 23 I/O 22 I/O 21 I/O 20 I/O 19
39 38 37
6 5 4 3 2 1 44 43 42 41 40 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC *ispEN/NC *SDI/IN 0 I/O 0 I/O 1 I/O 2 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 I/O 18 I/O 17 I/O 16 *MODE/IN 2 Y1/RESET VCC *SCLK/Y2 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 1016E pLSI 1016E
Top View
36 35 34 33 32 31 30 29
GND *SDO/IN 1
I/O 8
I/O 9 I/O 10
* Pins have dual function capability for ispLSI 1016E only (except pin 13, which is ispEN only). ** Pins have dual function capability which is software selectable.
0123A-isp1016
ispLSI 1016E 44-pin TQFP Pinout Diagram
**GOE 0/IN 3
I/O 27
I/O 26 I/O 25
I/O 24
GND I/O 23
I/O 22
44 43 42 41 40 39 38 37 36 35 34 I/O 28 I/O 29 I/O 30 I/O 31 Y0 VCC ispEN *SDI/IN 0 I/O 0 I/O 1 I/O 2 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22
GND *SDO/IN 1 I/O 8 I/O 9 I/O 10 I/O 11 I/O 3 I/O 4 I/O 5 I/O 6 I/O 7
I/O 21 I/O 20 I/O 19
I/O 11
I/O 3
I/O 4 I/O 5
I/O 6
I/O 7
33 32 31
I/O 18 I/O 17 I/O 16 *MODE/IN 2 Y1/RESET VCC *SCLK/Y2 I/O 15 I/O 14 I/O 13 I/O 12
ispLSI 1016E
Top View
30 29 28 27 26 25 24 23
* Pins have dual function capability. ** Pins have dual function capability which is software selectable.
0851-16E/TQFP
13
1996 ISP Encyclopedia
Specifications ispLSI and pLSI 1016E
Part Number Description
(is)pLSI Device Family ispLSI pLSI Device Number Speed 125 = 125 MHz fmax 100 = 100 MHz fmax 80 = 84 MHz fmax 1016E - XXX X XXX X Grade Blank = Commercial I = Industrial Package J = PLCC T44 = TQFP Power L = Low
0212/1016E
ispLSI and pLSI 1016E Ordering Information
COMMERCIAL
FAMILY fmax (MHz) 125 125 ispLSI 100 100 84 84 125 pLSI 100 84 tpd (ns) 7.5 7.5 10 10 15 15 7.5 10 15 ORDERING NUMBER ispLSI 1016E-125LJ ispLSI 1016E-125LT44 ispLSI 1016E-100LJ ispLSI 1016E-100LT44 ispLSI 1016E-80LJ ispLSI 1016E-80LT44 pLSI 1016E-125LJ pLSI 1016E-100LJ pLSI 1016E-80LJ PACKAGE 44-Pin PLCC 44-Pin TQFP 44-Pin PLCC 44-Pin TQFP 44-Pin PLCC 44-Pin TQFP 44-Pin PLCC 44-Pin PLCC 44-Pin PLCC
Table 2-0041A/1016E
INDUSTRIAL
FAMILY ispLSI fmax (MHz) 84 84 tpd (ns) 15 15 ORDERING NUMBER ispLSI 1016E-80LJI ispLSI 1016E-80LT44I PACKAGE 44-Pin PLCC 44-Pin TQFP
Table 2-0041B/1016E
14
1996 ISP Encyclopedia
Copyright (c) 1997 Lattice Semiconductor Corporation. E2CMOS, GAL, ispGAL, ispLSI, pLSI, pDS, Silicon Forest, UltraMOS, Lattice Semiconductor, L (stylized) Lattice Semiconductor Corp., L (stylized) and Lattice (design) are registered trademarks of Lattice Semiconductor Corporation. Generic Array Logic, ISP, ispATE, ispCODE, ispDOWNLOAD, ispGDS, ispDS, ispDS+, ispStarter, ispSTREAM, ispTEST, ispTURBO, Latch-Lock, pDS+, RFT, Total ISP and Twin GLB are trademarks of Lattice Semiconductor Corporation. ISP is a service mark of Lattice Semiconductor Corporation. All brand names or product names mentioned are trademarks or registered trademarks of their respective holders. Lattice Semiconductor Corporation (LSC) products are made under one or more of the following U.S. and international patents: 4,761,768 US, 4,766,569 US, 4,833,646 US, 4,852,044 US, 4,855,954 US, 4,879,688 US, 4,887,239 US, 4,896,296 US, 5,130,574 US, 5,138,198 US, 5,162,679 US, 5,191,243 US, 5,204,556 US, 5,231,315 US, 5,231,316 US, 5,237,218 US, 5,245,226 US, 5,251,169 US, 5,272,666 US, 5,281,906 US, 5,295,095 US, 5,329,179 US, 5,331,590 US, 5,336,951 US, 5,353,246 US, 5,357,156 US, 5,359,573 US, 5,394,033 US, 5,394,037 US, 5,404,055 US, 5,418,390 US, 5,493,205 US, 0194091 EP, 0196771B1 EP, 0267271 EP, 0196771 UK, 0194091 GB, 0196771 WG, P3686070.0-08 WG. LSC does not represent that products described herein are free from patent infringement or from any third-party right. The specifications and information herein are subject to change without notice. Lattice Semiconductor Corporation (LSC) reserves the right to discontinue any product or service without notice and assumes no obligation to correct any errors contained herein or to advise any user of this document of any correction if such be made. LSC recommends its customers obtain the latest version of the relevant information to establish, before ordering, that the information being relied upon is current. LSC warrants performance of its products to current and applicable specifications in accordance with LSC's standard warranty. Testing and other quality control procedures are performed to the extent LSC deems necessary. Specific testing of all parameters of each product is not necessarily performed, unless mandated by government requirements. LSC assumes no liability for applications assistance, customer's product design, software performance, or infringements of patents or services arising from the use of the products and services described herein. LSC products are not authorized for use in life-support applications, devices or systems. Inclusion of LSC products in such applications is prohibited. LATTICE SEMICONDUCTOR CORPORATION 5555 Northeast Moore Court Hillsboro, Oregon 97124 U.S.A. Tel.: (503) 681-0118 FAX: (503) 681-3037 http://www.latticesemi.com
February 1997

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